中圖分類號： TN402
文獻標(biāo)識碼： A
DOI：10.16157/j.issn.0258-7998.219805
中文引用格式： 賀愷華，丁學(xué)偉. 5 nm MSOA RapidPDK及物理實現(xiàn)[J].電子技術(shù)應(yīng)用，2021，47(8)：59-63，67.
英文引用格式： He Kaihua，Ding Xuewei. 5 nm physical implementation with MSOA RapidPDK[J]. Application of Electronic Technique，2021，47(8)：59-63，67.

5 nm physical implementation with MSOA RapidPDK

Abstract： Success in today′s electronics market place,most SoCs currently being developed have analog or mixed signal blocks, many so-called analog blocks actually have digital-control logic.Virtuoso-innovus flow with MSOA RapidPDK allows for all or parts of the physical hierarchy to pass back and forth between Virtuoso and Innovus easily without having to generate a DEF/GDS file. In this paper, we firstly describe the way to generate 5 nm RapidPDK, then use this PDK with digital flow to finish 5 nm IP design with custom lib. Additionally, this Virtuoso-innovus flow provides our analog designers with advanced techniques for 5 nm floorplanning, pin optimization, track generation and auto place & routing with RC extraction and timing analysis aware which will simplify the flow to enable virtuoso users to run 5 nm layout implementation, and also could help us to do full chip STA analysis

Key words : MSOA RapidPDK；5 nm；Virtuoso；Innovus