中圖分類號： TN402
文獻標識碼： A
DOI：10.16157/j.issn.0258-7998.229802
中文引用格式： 陳思雨，黃亞平，胡劼，等. 一種加速大規(guī)模模擬和射頻IC后仿真的驗證流程[J].電子技術應用，2022，48(8)：42-45.
英文引用格式： Chen Siyu，Huang Yaping，Hu Jie，et al. A verification flow on speed-up large-scale analog and RFIC post-layout simulations[J]. Application of Electronic Technique，2022，48(8)：42-45.

A verification flow on speed-up large-scale analog and RFIC post-layout simulations

Abstract： Recently, the functions and features implemented on Analog/RF ICs increases greatly which requires much more circuit blocks to be integrated into one single chip. On the other hand, with advanced node processes adopted, the post-layout netlist size of a single circuit block increases sharply. All of these pose a high demand on performance and efficiency of post-layout simulations and debugs. Except on adopt advanced Full-SPICE simulators, like Cadence Spectre X, to speed-up post-layout simulations, the choice and optimization method on post-layout input for simulator is another efficient methodology to speed-up overall post-layout verifications. This paper mainly focused on introducing a new post-layout simulation speed-up flow provided by Cadence Quantus SmartView and ADE Assembler with Spectre X,also comparisons with traditional flows are presented.

Key words : Quantus；SmartView；ADE Assembler；large-scale post-layout verification